1. Field of the Invention
The present invention relates to a comparator device for use in an A/D converter, and adapted to compare analog voltages.
2. Description of the Related Art
FIG. 17 shows the conventional comparator which is disclosed in A. G. F. Dingwall et al. "An 8 MHz CMOS Sub ranging 8 Bit A/D Converter," IEEE Journal Solid-State Circuits, Vol. SC-20, No. 6, December 1985, pp. 1138-1143. The comparator comprises a two inverter circuits which are connected in cascade, thereby to attain a gain greater than in the case where only one inverter circuit is used. More specifically, a reference voltage Vref is applied to the input of a switch S1, and an input voltage Vin is supplied to the input of another switch S2. The outputs of these switches S1 and S2 are connected by a capacitor C1 to the input of the first inverter circuit IV1. A switch S3 is connected between the input and output of the first inverter circuit IV1. The output of the inverter circuit IV1 is connected by a capacitor C2 to the input of the second inverter circuit IV2. A switch S4 is connected between the input and output of the second inverter circuit IV2. A control signal .phi.AZ controls the switches S1, S3, and S4. A control signal .phi.AMP controls the switch S2.
First, the control signal .phi.AZ turns on the switches S1, S3, and S4. The potentials across the capacitors C1 and C2 are then Vc1 - Vref and Vc2-Vc1, respectively, where Vc1 is the operation voltage of the inverter circuit IV1, and Vc2 is that of the inverter circuit IV2.
Next, the control signal .phi.AZ turns off the switches S1, S3, and S4, and the control signal .phi.AMP turns on the switch S2. Then, the input voltage V1i and output voltage V1o of the inverter circuit IV1, and the input voltage V2i and output voltage V2o of the the inverter circuit IV2 will be: ##EQU1## where -A1 is the gain of the first inverter circuit IV1, and -A2 is the gain of the second inverter circuit IV2.
Obviously, the inverter circuit IV2 outputs a voltage which has been generated by amplifying the input voltage by the product of the gains of the inverter circuits IV1 and IV2, and has an offset voltage of "0." To enhance the gain of the comparator, more inverter circuits are coupled in cascade.
The time tAMP which the comparator shown in FIG. 17 needs to compare the input voltage Vin with the reference voltage Vref is substantially as long as tAMP1 +tAMP2, where tAMP1 is the time which lapses until the output voltage of the inverter circuit IV1 is determined after the input voltage thereof has been detected, and tAMP2 is the time which lapses until the output voltage of the inverter circuit IV2 is determined after the input voltage thereof has been detected. The time tAMP is about twice as long as the comparator should need to compare the input voltage Vin with the reference voltage Vref if it had only one inverter circuit. If the comparator comprised three or more inverter circuits to acquire a greater gain, the time tAMP would be inevitably longer. The same holds true of a comparator which comprises differential amplifiers.
FIG. 18 shows the positive-feedback comparator which is disclosed in ITEJ Technical Report, Vol. 14, NO. 32, pp. 7-12. The positive-feedback comparator has a gain which is theoretically infinite, and can compare an input voltage with a reference voltage within a short time. This comparator, however, has its offset not compensated for. Hence, if the metal oxide semiconductor field-effect transistors (MOSFETs) Q42 and Q43 have no identical characteristic, or if the MOSFETs Q44 and Q45 have no identical characteristic, there will be generated an offset voltage. Although the positive-feedback comparator operates at high speed, its offset voltage can hardly be minimized.